FPGA LCD Display Design
- Apr 19, 2018 -


The display panel manufactured by the LCD liquid crystal display is widely used in military equipment. This design adopts the Spartan-3E FPGA as the hardware. The 2&TImes;16 character LCD incorporates a Sitronix ST7066U graphics controller to realize the character or Chinese character of the LCD display. Full-screen display, full-screen mobile display, and single-character display on the screen. All functions are implemented in VHDL language to meet LCD display requirements and achieve a variety of display effects.

Due to its small size, light weight, and low power consumption, LCD liquid crystal displays have a wide range of applications. For example, as display panels for aircrafts, tanks, and ships, the space occupied by the original CRT display can be reduced, the weight of the device can be reduced, and the mobility can be enhanced.

This design uses a character LCD with an embedded Si.tronix ST7066U graphic controller on the Spartan-3E development board, which implements: (1) Single character display at any position and full-screen and full-screen display of characters; (2) The display of custom characters (characters) and the full screen movement display of individual characters. Among them, the graphics controller [1] is responsible for receiving control commands and data and sending it to the LCD display.

1 Sitronix ST7066U Graphics Controller

The controller has three internal storage spaces, DD RAM, CGROM, and CG RAM, which should be initialized before sending data.

(1) DD RAM (display data RAM)

The character code is stored. Physically, the DD RAM has a total of 80 character positions, each line has 40 characters, but only 16 can be displayed and the remaining 24 are not displayed. Before reading or writing, the address counter needs to be initialized. The address counter can be kept constant or automatically incremented or decremented by 1 after reading or writing.

(2) CG ROM (Character Generator ROM)

A font bitmap containing each pre-determined character.

(3) CG RAM (character generator RAM)

Contains 8-bit custom character bitmaps. Each custom character bit consists of 5 points in 8-bit bitmaps. The specific usage is the same as DD RAM.

1.1 Interface Signals with FPGA

LCD and FPGA interface signals [2] are: (1) enable signal LCD_E; (2) register select signal LCD_RS; (3) read/write control signal LCD_RW; (4) four LCD data lines and StrataFlash data line SF_D Reuse 11:8.

1.2 Timing Analysis

The data value of SF_D 11:8, LCD_RS, LCD_RW must be established and stable at least 40 ns before LCD_E goes high, and LCD_E remains high for at least 230 ns. In many applications, LCD_RW is always low because data is not normally read from the display.

As shown in Figure 1, the data is transmitted in 8-bit format and is divided into high 4 bits and low 4 bits. The first high 4 bits and then the low 4 bits have an interval of at least 1us. An 8-bit write operation has a minimum interval of 40 us before the next communication, and the delay needs to increase to 1.64 ms after the clear command.

FPGA-based LCD LCD Design

Figure 1 character LCD interface timing diagram

2 data display design

2.1 Flow Chart

As shown in Figure 2, LCD data display includes power-on initialization, configuration display, write data to the display, and the initial address should be set before writing data.

FPGA-based LCD LCD Design

Figure 2 LCD display flow chart


The development board crystal is 50 MHz.